AMDGPU関連用語略称まとめ
Update: 2021/05/21 14:03 JST
個人的なメモ
Software
| Abbr | Full | memo |
|---|---|---|
| UMD | User Mode graphics Drivers | |
| KMD | Kernel Mode graphics Drivers | |
| KDG | Kernel Graphics Driver | |
| KMS | Kernal Mode Setting | drm1 |
| TTM | Translation Table Maps | drm1 |
| MMU | Memory Managiment Unit | |
| MN | MMU Notifier | drm1 |
| GEM | Graphics Execution Manager | drm1 |
| GTT | Graphics Address Remapping Table | drm1 |
| PD | Primitive Discard | RadeonSI /RADV |
| HSA | Heterogeneous System Architecture | |
| HMM | Heterogeneous Memory Management | |
| OA | Ordered Append | |
| MSI | Massage Signaled Interrupts | drm1 |
| EMU | Emulation mode | drm1 |
| ABM | Adaptive Backlight Management | drm1 |
| BAPM | Bidirectional Application Power Management | |
| LBPW | Load Balancing Per Watt | |
| DPM | Dynamic Power Management | |
| DPMS | DMP State? | |
| CWSR | Compute Wave Save and Restore | drm1 |
| GWS | Global Wave Sync | drm1 |
| CRAT | Component Resource Association Table | GPU cache info |
| VF | Virtual Function | MxGPU |
| DPBB | Deferred Primitive Batch Binning | DSBR, partial primitive binning |
| DFSM | ? | DSBR, full primitive binning |
| PBB | Pipeline Binning2 |
Hardware
| Abbr | Full | memo |
|---|---|---|
| SE | Shader Engine | |
| SA/SH | Shader Array | GCN(1SE =1SA =16CU), RDNA(1SE =2SA =10WGP =20CU) |
| HWS | Hardware Schedulers | |
| ACE | Asynchronous Compute Engine | |
| RB | Render Backend | =4 ROPs |
| ROP | Render Output Pipeline | |
| GMC | Graphics(GFX?) Memory Controller | |
| GDS | Global Data Share | |
| LDS | Local Data Share | |
| DMA | Direct Memory Access | |
| SDMA | System DMA | |
| GCP | Graphics Command Processor | |
| MCBP | Mid Command Buffer Preemption | |
| CS | Command Stream | |
| EOP | End Of Packet | |
| SMU | System Manasgement Unit | |
| PG | Powergating | |
| RLC | Rear left Center? | |
| PFP | Prefetch Parser | |
| CE | Constant Engine | |
| DE | Dispatch Engine | |
| ME | Micro Engine | |
| MES | Micro Engine Scheduler | GFX10? |
| MEC | Micro Engine Compute? | |
| PSP | Platform Security Processor | |
| RAP | Register Access Policy3 | |
| SDP | Scalable Data Port | |
| PA | Primitive Assembly | |
| IA | Input Assembly | |
| HTILE | Hi-Z Depth Compression | |
| IB | Indirect Buffer | = GPU command buffer |
| LRU | Least Recently Used | |
| CGPG | Coarse Grained PoweGating | |
| UVD | Unified Video Decoder | |
| VCE | Video Compression (/Codec) Engine | |
| VCN | Video Core Next | |
| DC | Display Core | |
| PSR | Panel Self-Refresh | eDP PowerSave |
| DCE | Display Core Engine? | |
| DMCUB | Display Micro Controller Unit B | |
| HBCC | High Bandwidth Cache Controller | GFX9+ |
| DSBR | Draw Stream Binning Rasterrizer | GFX9+ |
| SGPR | Scalar General-Purpose Register | |
| VGPR | Vector General-Purpose Register | |
| ALU | Arithmetc Logic Unit | |
| SPI | Shader Processor Interpolator / Shader Processor Input | |
| PRT | Partially Resident Textures | |
| DIO | Display IO | DCN3 |
| OPP | Output Plane Processing | DCN3 |
| MPC | Multiple pipe and plane combine | DCN3 |
| DPP | DCN3 | |
| HUBBUB | DCN memory HUB interface /DCN3 | |
| MMHUBBUB | Multimedia HUB interface /DCN3 | |
| HUBP | Display to data fabric interface /DCN3 | |
| DWB | Display Writeback | DCN3 |
| DML | Display mode library | DCN3 |
| DMUB | Display Micro-Controller Unit4 | |
| AMFT | Audio formating | |
| VPG | Video Package ganerator | |
| SPL | Security patch level | |
| PC_LINES | Parameter Cache Lines? | |
| HDP | Host Data Path5 | |
| MGCG | Medium Grain Clock Gating | |
| MGLS | Medium Grain Light Sleep | |
| IH | Interrupt Handler6 | |
| TMR | Trust Memory Region7 | |
| SQ | (Distributed) Sequencer |
Other
| Abbr | Full | memo |
|---|---|---|
| CDIT | Component locality Distance Information Table | |
| AO | Always On | |
| DCC | Delta Color Compression | lossless |
| DSC | Display Stream Compression | DCN 2.0+ |
| TDP | Thermal Design Power | |
| TBP | Typical Board Power | |
| TMZ | Trusted Memory Zone | |
| DWB | Display WriteBack | |
| RAS | Reliability, Availability, Serviceability | |
| HDCP | Highbandwidth Digital Content Protection | |
| TA | Texture Address /Trusted Application?8 | |
| TC | Texture Cache? | |
| TCA | Texture Cache Arbiter ??? | |
| TCC | Texture Channel Cache?9 | == L2cache |
| TCP | Texture Cache Private ??? | GCN L1$, RDNA L0$ |
| BACO | Bus Active, Chip Off10 | |
| BOCO | Bus Off, Chip Off10 | |
| OPN | ordering Part Number | |
| ULV | Ultra Low Voltage11 | |
| GL2a | GL2 Arbiter12 | == TCA13 (Navi10 = 4, Navi14 = 2) |
| GL2c | == TCC13 (Navi10 = 16, Navi14 = 8) |
|
| SC | Shader Compiler? / Scan Converter14 | Rasterizer |
| SX | Shader Export14 | |
| GPA | Guest Pysical Address15 | |
| EDC | Error Correction and Detection16 | |
| SPM | Streaming Performance Counter17 | |
| ICD | Installable Client Driver | |
| MALL | Memory Access (at) Last Level18 | GFX10.3+ |
| SRD | Shader Resource Descriptor19 | |
| PRT | Partially Resident Texture20 | |
| TDR | Timeout Detection and Recovery ?21 |
- drm/amdgpu AMDgpu driver — The Linux Kernel documentation [return]
- xgl/settings_xgl.json at 0d602bbcfa1a86fd52f66966554b05e384a10d38 · GPUOpen-Drivers/xgl [return]
- drm/amdgpu: add RAP TA header file [return]
- drm/amd/display: Add DCN3 DMUB [return]
- drm/amdgpu: add the HDP 4.0 register headers [return]
- drm/amdgpu: add navi10 ih ip block (v3) [return]
- drm/amdgpu:add tmr mc address into amdgpu_firmware_info [return]
- drm/amdgpu/psp: add structure for xgmi ta and its shared buffer [return]
- [radeonsi] Tahiti LE: GFX block is not functional, CP is okay (#1208) · Issues · Mesa / mesa · GitLab [return]
- drm/amdgpu: rename amdgpu_device_is_px to amdgpu_device_supports_boco (v2) [return]
- drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid [return]
- pal/gfx9PerfCtrInfo.cpp at c9937b277c491a55c689eec7cdd48fb238b8004c · GPUOpen-Drivers/pal [return]
- pal/devDriverUtil.cpp at a3a42838c576cc219e61500bc469a4a05ce0db68 · GPUOpen-Drivers/pal [return]
- AMD PowerPoint- White Template - nordic-game-2019-triangles-are-precious.pdf [return]
- drm/amdgpu: use gpu virtual address for interrupt packet write space for vangogh [return]
- drm/amdgpu: add EDC support for CZ (v3) [return]
- https://github.com/GPUOpen-Drivers/pal/blob/477c8e78bc4f8c7f8b4cd312e708935b0e04b1cc/inc/core/palPerfExperiment.h#L92 [return]
- [PATCH 2/3] drm/amdgpu: add support to configure MALL for sienna_cichlid (v2) [return]
- pal/palCodingStandards.md at 4ae736bdbc5d5dee59851ac564c5e21d807b44b0 · GPUOpen-Drivers/pal [return]
- pal/palDeveloperHooks.h at c9937b277c491a55c689eec7cdd48fb238b8004c · GPUOpen-Drivers/pal [return]
- AMD_APP_SDK_Release_Notes_Developer.fm - AMD_APP_SDK_Release_Notes_Developer.pdf [return]
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